1. Field of the Invention
The present invention relates to a clock generating circuit and a semiconductor device including the same, and more particularly relates to a clock generating circuit that generates a phase-adjusted internal clock signal such as a DLL (Delay Locked Loop) circuit, and a semiconductor device including the clock generating circuit. The present invention also relates to a data processing system including the semiconductor device.
2. Description of Related Art
In recent years, synchronous memories that operate synchronously with a clock have been widely used as main memories of personal computers and the like. Particularly, because DDR (Double Data Rate) synchronous memories need to accurately synchronize input/output (I/O) data with an external clock signal, a DLL circuit that generates an internal clock signal synchronously with the external clock signal is essential for the synchronous memories see Japanese Patent Application Laid-open No. 2008-217947 or U.S. Patent Application Publication No. 2008/0218227).
A DLL circuit includes a counter circuit of which a count value is updated based on phases of an external clock signal and an internal clock signal, and a delay line that generates an internal clock signal by delaying an external clock signal based on a count value of the counter circuit. The initial value of a counter circuit is often set at a minimum value or a maximum value, and in this system, the counter circuit is caused to forcibly count up or count down regardless of a phase determination result immediately after initializing the DLL circuit.
FIG. 8 is an explanatory diagram of an operation of a DLL circuit according to the above system.
FIG. 8 is a waveform diagram showing a relationship between a waveform of an external clock signal CK and an internal clock signal LCLK (not shown) as an output signal of a DLL circuit. As shown in FIG. 8, when a rising edge of the internal clock signal LCLK is at a position of a symbol A at an initializing time of the DLL circuit, the DLL circuit can be locked in a shortest time when a phase of the internal clock is synchronized with a rising edge #0 of an external clock signal CK by advancing the phase of the internal clock signal ahead the external clock signal CK (by decreasing a delay value of a delay line as a variable delay circuit by setting a counter circuit within the DLL circuit to count down). However, when an initial value of the counter circuit is already set at a minimum value (that is, when the delay line as a variable delay circuit is set at a minimum delay value), the counter circuit cannot further count down (a delay value cannot be further decreased). Therefore, from a time axis viewpoint, a phase of the internal clock signal needs to be delayed (the counter circuit needs to count up) such that a phase of the internal clock is synchronized with a next rising edge #1 of the external clock signal CK. That is, by a delay control of the variable delay circuit of the DLL circuit after initializing the DLL circuit, in a phase adjusting control up to “lock” indicating that a phase of the external clock signal CK matches a phase of the internal clock signal LCLK, the counter circuit needs to forcibly count up regardless of a phase comparison result showing count down, when a rising edge of the internal clock signal is located in a region B (specifically, a High period of the external clock signal CK) during an initial phase-control period of repetitively performing a delay adjustment of the delay line following a phase comparison and a result thereof. In this example, the phase comparison is performed to the rising edge of the external clock signal CK. In the following explanations, when a phase comparison result is “showing count down”, it can be simply called “count down”, and when a phase comparison result is “showing count up”, it can be simply called “count up”. A lock indicating that a phase of the external clock signal matches a phase of the internal clock signal is also called “DLL lock”. The term “match (matching)” also means a case that a result of plural phase comparisons matches a predetermined result pattern from a time axis viewpoint, and it should be taken into account that the term does not simply mean a case that a result of a phase comparison at one time matches a predetermined result pattern.
Such a forcible count up operation naturally needs to be cancelled when the DLL circuit is locked. Therefore, a forcible count up operation is finished and count down or count up is performed as usual based on a result of a phase comparison, when a characteristic that appears at the time of locking the DLL circuit is detected, that is, when the internal clock signal approaches the rising edge #1 of the external clock signal immediately before reaching the lock and when a characteristic that a result of a phase comparison is an alternate repetition of count down and count up is detected.
However, the above characteristic that appears at a DLL locking time sometimes also appears when noise is received such as when a power source varies not only when the DLL is locked. For example, when a rising edge of the internal clock signal LCLK is still located in the region B shown in FIG. 8 and when a result of a phase comparison is a temporary change from count down to count up due to the influence of various noises despite a period of performing forcible count up regardless of a phase comparison result (count down), the result of a phase comparison is returned to the count down again when noise disappears. Therefore, there may be a false recognition that this shifting of a comparison result is a DLL lock (an edge of the internal clock signal reaches the rising edge #1 of the external clock signal CK). As another example, a phase comparison result returns to the count down again when a rising edge of the internal clock signal returns from a region C to the region B shown in FIG. 8 due to the influence of noise immediately after the rising edge of the internal clock signal moves from the region B to the region C (that is, immediately after a comparison result changes from count down to count up). Therefore, there may be a false recognition that this shifting of a comparison result is a DLL lock. When these false recognitions occur, a forcible count up operation is cancelled, and thus count down is progressed and the phase is advanced toward the rising edge #0.
However, in this example, a position of the symbol A corresponds to a minimum value of the counter circuit, and the counter circuit cannot count down any more. That is, the counter circuit is stuck at the position of the symbol A, and further phase adjustment cannot be made. That is, this phase adjusting control is stuck because the phase does not reach the rising edge #0 of the external clock signal even when the delay line is set at a minimum delay value as described above.
Such a problem occurs not only in DLL circuits but also commonly occurs in clock generating circuits that adjust a phase of an internal clock signal based on a result of a phase comparison.